MOSFET Fundamentals: Beyond the Switch Model

In the last post, I discussed my decision to return to school to stop treating the schematic like a black box. Today, we are opening that box. We are going back to the fundamental building block: the MOSFET. To really understand design, we need to look at how a MOSFET turns on and the equations that govern it.

How a Transistor Actually Turns ON

Consider an NMOS device. You have a P-type substrate (lots of Holes) and two N-type regions (Source and Drain). When you apply a positive voltage to the Gate ($V_{GS} > 0$), two things happen:

• Depletion: The positive charge on the Gate repels the Holes (majority carriers) in the substrate directly underneath the oxide. This leaves behind immobile negative ions, creating a Depletion Region.
• Inversion: As you increase $V_{GS}$, the potential at the surface becomes positive enough to attract Electrons (minority carriers) from the bulk and the Source/Drain regions. These electrons pile up under the oxide.

When the concentration of these electrons exceeds the concentration of holes in the bulk, the surface is “inverted” from P-type to N-type. This forms a conductive channel.

Regions of Operation

As Analog engineers, we live and die by these regions. Here is the breakdown for both devices.

NMOS Equations

• Threshold: $V_{TN}$
• Condition to turn on: $V_{GS} > |V_{TN}|$

a) Triode/Linear: Condition: $V_{DS} < (V_{GS} - V_{TN})$

Current equation: $I_{D} = \mu_{n}C_{ox}\frac{W}{L}\left[(V_{GS}-V_{TN})V_{DS}-\frac{V_{DS}^{2}}{2}\right]$

The channel exists continuously from Source to Drain.

b) Saturation: Condition: $V_{DS} \ge (V_{GS} - V_{TN})$

$I_{D} = \frac{1}{2}\mu_{n}C_{ox}\frac{W}{L}(V_{GS}-V_{TN})^{2}$

The channel pinches off at the drain side. Current becomes (mostly) independent of $V_{DS}$.

PMOS Equations

For PMOS, voltages are usually referenced to the Source rather than Ground.

• Threshold: $V_{TP}$
• Condition to turn on: $V_{SG} > |V_{TP}|$

a) Triode/Linear: Condition: $V_{SD} < (V_{SG} - |V_{TP}|)$

$I_{D} = \mu_{p}C_{ox}\frac{W}{L}\left[(V_{SG}-|V_{TP}|)V_{SD}-\frac{V_{SD}^{2}}{2}\right]$

b) Saturation: Condition: $V_{SD} \ge (V_{SG} - |V_{TP}|)$

$I_{D} = \frac{1}{2}\mu_{p}C_{ox}\frac{W}{L}(V_{SG}-|V_{TP}|)^{2}$

Note:

If you plot $I_D$ vs $V_{DS}$ (Output Characteristics) and $I_D$ vs $V_{GS}$ (Transfer Characteristics), you get the standard curves we are all familiar with. Here’s one mistake which some people make while trying to get the plots. When simulating an NMOS, it is straightforward: The Source is usually Ground, so sweeping $V_{Gate}$ works perfectly. However, when simulating a PMOS, a common error is to connect the PMOS Source to VDD, but sweep the Gate voltage with respect to Ground (0 to VDD). Remember it is the Source-to-Gate Voltage ($V_{SG}$) and not just the Gate Voltage ($V_G$), that controls a PMOS transistor!

MOSFET as a Switch

Here is a question I stumbled on early in my career: Which terminal is the Source? The answer depends on the voltages applied, as the device structure is symmetrical. To determine the source terminal in an NMOS transistor, we must look at the flow of majority carriers. Consider a scenario where one terminal is connected to $V_{dd}$ and the other to $V_{out}$. Conventional current flows from the higher potential ($V_{dd}$) to the lower potential ($V_{out}$). However, since the charge carriers in an NMOS are electrons, they flow in the direction opposite to conventional current—from $V_{out}$ towards $V_{dd}$. Because the Source is defined as the terminal that supplies carriers into the channel, the terminal at the lower potential ($V_{out}$) functions as the Source, while the terminal at the higher potential ($V_{dd}$) functions as the Drain.

That is the rigorous physics explanation. But if you don’t want to perform mental gymnastics every time you look at a schematic, here is the cheat code: Just remember that for an NMOS the terminal at lower potential is the Source! Similarly, for a PMOS, the terminal at higher potential is the source!

This physics dictates why they pass logic levels differently.

NMOS Passing a “1” (Weak 1): If you put $V_{DD}$ on the Gate and try to pass $V_{DD}$ from Drain to Source, the Source voltage rises. As $V_{Source}$ rises, $V_{GS}$ drops. When $V_{Source}$ reaches $V_{DD} - V_{TN}$, the device cuts off. It can never pull all the way to $V_{DD}$.

PMOS Passing a “0” (Weak 0): As the drain drops, $|V_{GS}|$ decreases. The PMOS stops conducting before it hits true ground (stops at $|V_{TP}|$). This is why we use NMOS to pull down (Strong 0) and PMOS to pull up (Strong 1) in CMOS logic.

Small Signal Analysis

Finally, let’s look at the Saturation equations again. In reality, increasing $V_{DS}$ slightly increases current because the effective channel length shortens. This is Channel Length Modulation. (We will discuss this and other short channel effects in depth separately). We update the equation:

NMOS: $I_{D} = \frac{1}{2}\mu_{n}C_{ox}\frac{W}{L}(V_{GS}-V_{TN})^{2}(1+\lambda V_{DS})$

PMOS: $I_{D} = \frac{1}{2}\mu_{p}C_{ox}\frac{W}{L}(V_{SG}-|V_{TP}|)^{2}(1+\lambda V_{SD})$

A MOSFET takes an input Voltage ($V_{GS}$) and converts it to an output Current ($I_D$). This type of device is called as a Transconductor. We define Transconductance ($g_m$) as the change in current for a tiny change in voltage: Mathematically, transconductance is the derivative of the drain current ($I_D$) with respect to the gate-source voltage ($V_{GS}$), assuming the drain-source voltage ($V_{DS}$) is constant.

$g_m = \frac{\partial I_D}{\partial V_{GS}} \bigg|_{V_{DS}}$

There are 3 formulas frequently used to calculate $g_m$.

In terms of Drain Current ($I_D$): $g_m = \sqrt{2 \mu_n C_{ox} \frac{W}{L} I_D}$

In terms of Overdrive Voltage ($V_{GS} - V_{th}$): $g_m = \mu_n C_{ox} \frac{W}{L} (V_{GS} - V_{th})$

In terms of $I_D$ and Overdrive: $g_m = \frac{2 I_D}{V_{GS} - V_{th}}$

Small Signal Model

Calculating non-linear square laws by hand for complex circuits is difficult. So, we use the Small Signal Model under specific assumptions:

• The input AC signal ($v_{gs}$) is small enough such that it does not change the overdrive voltage and consequently the drain current by a lot i.e. ($v_{gs}$) very very less than ($V_{GS} - V_{TN}$).
• Certain bias voltage is applied to the device.

To draw the small signal model:

• Short all independent DC Voltage sources to Ground (VDD becomes AC Ground).
• Open all independent DC Current sources.
• Replace the transistor with its linear model: A voltage-controlled current source ($g_m v_{gs}$) in parallel with an output resistance $r_o$ (representing channel length modulation).

This creates a linear circuit that we can solve using basic KCL/KVL.

DON’T PANIC!

If the small-signal model looks intimidating at first, don’t worry it is the most powerful tool we have for breaking down complex behavior into solvable linear equations.

The good news is that you don’t need to draw a small-signal model for every single transistor in a massive schematic. As you get comfortable, you will learn to recognize patterns. We analyze simple building blocks once, and then reuse those known results to intuitively understand much larger, more complicated circuits.

Master the model now, and you will eventually be able to “see” the gain and impedance of a circuit just by looking at the schematic.